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| LTC1735 High Efficiency Synchronous Step-Down Switching Regulator December 1998 FEATURES s s s s s s s s s DESCRIPTIO s s s s s s Dual N-Channel MOSFET Synchronous Drive Synchronizable/Programmable Fixed Frequency Wide VIN Range: 3.5V to 36V Operation VOUT Range: 0.8V to 6V Very Low Dropout Operation: 99% Duty Cycle 1% 0.8V Reference Internal Current Foldback Output Overvoltage Crowbar Protection Latched Short-Circuit Shutdown Timer with Defeat Option Forced Continuous Control Pin Optional Programmable Soft-Start Remote Output Voltage Sense Logic Controlled Micropower Shutdown: IQ < 20A LTC1435 Pin Compatible with Minor Component Changes Available in 16-Lead Narrow SSOP and SO Packages The LTC(R)1735 is a synchronous step-down switching regulator controller that drives external N-channel power MOSFETs using a fixed frequency architecture. Burst ModeTM operation provides high efficiency at low load currents. A maximum high duty cycle limit of 99% provides low dropout operation, which extends operating time in battery operated systems. The precision 0.8V 1% reference is compatible with future microprocessor generations. The operating frequency (synchronizable up to 500kHz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. A forced continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling Burst Mode operation when the main output is lightly loaded. Protection features include internal foldback current limiting, output overvoltage crowbar and optional shortcircuit shutdown. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a trademark of Linear Technology Corporation. APPLICATIO S s s s s Notebook and Palmtop Computers, PDAs Cellular Telephones and Wireless Modems DC Power Distribution Systems Battery Chargers TYPICAL APPLICATIO CSS 0.1F CC 330pF RC 10k COSC COSC 43pF TG RUN/SS BOOST ITH SW LTC1735 VIN SGND 100pF VOSENSE BG SENSE - 1000pF SENSE + PGND INTVCC DB CMDSH-3 L1 1.5H CB 0.22F M1 Si4410DY VIN 7V TO 22V + CIN 10F 30V X2 RSENSE 0.006 VOUT 1.6V 9A PEAK + 4.7F M2 Si4420DY D1 MBRS340 Figure 1. High Efficiency Step-Down Converter Specifications on this data sheet are preliminary only, and subject to change without notice. Contact the manufacturer before finalizing a design using this part. U R1 20k 1% R2 20k 1% U U + COUT 180F 4V X2 1735 TA01 1 LTC1735 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COSC 1 RUN/SS 2 ITH 3 FCB 4 SGND 5 VOSENSE 6 SENSE - 7 SENSE + 8 16 TG 15 BOOST 14 SW 13 VIN 12 INTVCC 11 BG 10 PGND 9 EXTVCC Input Supply Voltage (VIN).........................36V to - 0.3V Topside Driver Supply Voltage (BOOST)....42V to - 0.3V Switch Voltage (SW).....................................36V to - 5V EXTVCC Voltage ...........................................7V to - 0.3V Boosted Driver Voltage (BOOST - SW) .......7V to - 0.3V SENSE +, SENSE - Voltages .......... 1.5 (INTVCC) to - 0.3V FCB Voltage ............................(INTVCC + 0.3V) to - 0.3V ITH, VOSENSE Voltages ...............................2.7V to - 0.3V RUN/SS Voltages .........................................7V to - 0.3V Peak Driver Output Current <10s (TG, BG) .............. 3A INTVCC Output Current ......................................... 50mA Operating Ambient Temperature Range LTC1735C................................................ 0C to 70C LTC1735I ............................................ - 40C to 85C Junction Temperature (Note 2) ............................. 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C ORDER PART NUMBER LTC1735CGN LTC1735CS LTC1735IGN LTC1735IS GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO TJMAX = 125C, JA = 140C/W (GN) TJMAX = 125C, JA = 110C/W (S) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS SYMBOL IIN VOSENSE VOSENSE VLINEREG VLOADREG PARAMETER Feedback Current Feedback Voltage Reference Voltage Line Regulation Output Voltage Load Regulation Main Control Loop TA = 25C, VIN = 15V, VRUN/SS = 5V unless otherwise noted. MIN TYP 10 q CONDITIONS (Note 3) (Note 3) VIN = 3.6V to 30V (Note 3) (Note 3) Measured in Servo Loop; VITH = 0.5V Measured in Servo Loop; VITH = 2V VFCB = 0.8V (Note 4), EXTVCC = 5V 3.6V < VIN < 30V VRUN/SS = 0V, 3.6V < VIN < 15V VRUN/SS, Ramping Positive VRUN/SS, Ramping Negative VRUN/SS = 0V Soft Short Condition, VOSENSE = 0.5V, VRUN/SS = 2V VOSENSE = 0.5V, VRUN/SS = 3V Measured at VIN Pin VOSENSE = 0.6V VSENSE- = VSENSE+ = 0V Tested with a Square Wave VITH = 1.75V, (Note 6) q q q MAX UNITS nA 0.792 0.8 0.002 0.2 - 0.2 0.8 - 0.25 0.86 450 15 1.3 3.5 2 -3 3 3.5 75 68 180 0.808 VFCB IFCB VOVL IQ Forced Continuous Threshold Forced Continuous Current Feedback Overvoltage Lockout Input DC Supply Current Normal Mode Shutdown Run Pin Start Threshold Run Pin Begin Latchoff Threshold Soft-Start Charge Current RUN/SS Discharge Current Shutdown Latch Disable Current Undervoltage Lockout Maximum Current Sense Threshold Sense Pins Total Source Current Minimum On-Time VRUN/SS VRUN/SS IRUN/SS ISCL ISDLHO UVLO VSENSMAX ISENSE tON(MIN) 2 U V %/V % % V A V A A V V A A A V mV A ns W U U WW W LTC1735 ELECTRICAL CHARACTERISTICS SYMBOL TG tr TG tf BG tr BG tf VINTVCC VLDO(INT) VLDO(EXT) VEXTVCC Oscillator fOSC fH/fOSC fFCB(SYNC) Oscillator Frequency Maximum Sync Frequency Ratio FCB Pin Threshold For Sync PARAMETER TG Transition Time: Rise Time Fall Time BG Transition Time: Rise Time Fall Time Internal VCC Voltage Internal VCC Load Regulation EXTVCC Drop Voltage EXTVCC Switchover Voltage TA = 25C, VIN = 15V, VRUN/SS = 5V unless otherwise noted. MIN TYP 50 50 50 50 5.2 0.15 150 4.7 300 1.3 1.2 Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: Oscillator frequency is tested by measuring the COSC charge current (IOSC) and applying the formula: -1 8.477(1011) 1 1 fOSC = + COSC (pF) + 11 ICHG IDIS CONDITIONS CLOAD = 3000pF CLOAD = 3000pF CLOAD = 3000pF CLOAD = 3000pF ICC = 20mA, 6V < VIN < 30V, VEXTVCC = 4V ICC = 0 to 20mA, VEXTVCC = 4V ICC = 20mA, VEXTVCC = 5V ICC = 20mA, EXTVCC Ramping Positive (Note 5), COSC = 43pF Ramping Positive MAX UNITS ns ns ns ns V % mV V kHz V Internal VCC Regulator The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: LTC1735CS, LTC1735IS: TJ = TA + (PD * 110 C/W) LTC1735CGN, LTC1735IGN: TJ = TA + (PD * 140C/W) Note 3: The LTC1735 is tested in a feedback loop that servos VOSENSE to the balance point for the error amplifier (VITH = 0.8V). Note 6: The minimum on-time condition corresponds to an inductor peakto-peak ripple current 40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). PI FU CTIO S COSC (Pin 1): External capacitor COSC from this pin to ground sets the operating frequency. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at this pin sets the ramp time to full output current. The time is approximately 0.5s/F. Forcing this pin below 1.3V causes the device to be shutdown. In shutdown all functions are disabled. Latchoff over current protection is also invoked via this pin as described in the Applications Information section. ITH (Pin 3): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 2.4V. FCB (Pin 4): Forced Continuous/Synchronization Input. Tie this pin to ground for continuous synchronous operation, to a resistive divider from the secondary output when using a secondary winding or to INTVCC to enable Burst Mode operation at low load currents. Clocking this pin with a signal above 1.5VP-P disables Burst Mode operation but allows cycle-skipping at low load currents and synchronizes the internal oscillator with the external clock. SGND (Pin 5): Small-Signal Ground. Must be routed separately from other grounds to the (-) terminal of COUT. VOSENSE (Pin 6): Receives the feedback voltage from an external resistive divider across the output. SENSE - (Pin 7): Connects to the (-) input of the Current Comparator. SENSE + (Pin 8): The (+) Input to the Current Comparator. Built-in offsets between SENSE - and SENSE + pins in conjunction with RSENSE set the current trip threshold. U U U 3 LTC1735 PI FU CTIO S EXTVCC (Pin 9): Input to the Internal Switch Connected to INTVCC. This switch closes and supplies VCC power whenever EXTVCC is higher than 4.7V. See EXTVCC connection in the Applications Information section. Do not exceed 7V on this pin. PGND (Pin 10): Driver Power Ground. Connects to the source of bottom N-channel MOSFET, the anode of the Schottky diode, and the (-) terminal of CIN. BG (Pin 11): High Current Gate Drive for Bottom NChannel MOSFET. Voltage swing at this pin is from ground to INTVCC. INTVCC (Pin 12): Output of the Internal 5.2V Regulator and EXTVCC Switch. The driver and control circuits are powered from this voltage. Must be closely decoupled to power ground with a minimum of 4.7F tantalum or other low ESR capacitor. VIN (Pin 13): Main Supply Pin. Must be closely decoupled to power ground. SW (Pin 14): Switch Node Connection to Inductor and Bootstrap Capacitor. Voltage swing at this pin is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (Pin 15): Supply to Topside Floating Driver. The bootstrap capacitor is returned to this pin. Voltage swing at this pin is from a diode drop below INTVCC to (VIN + INTVCC). TG (Pin 16): High Current Gate Drive for Top N-Channel MOSFET. This is the output of a floating driver with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. FU CTIO AL DIAGRA COSC COSC 1 SGND 5 SYNC C OSC + 0.86V - 0V 6 R1 R2 - + EA gm =1.4m 0.8V SD RUN SOFTSTART + OVERCURRENT LATCH-OFF RC RUN/SS CSS 2 CC 3 ITH 2A 6V 4 VOSENSE VFB 0.86V 4(VFB) SLOPE COMP W U U U U U VIN 13 VIN 0.8V REF 0.25A - + 1.2V FORCE BOT DROP OUT DET S Q R TOP ON 0.55V + - 2.4V 2k ICMP I1 - + 45k 45k SD - + I2 IREV VOUT BOT INTVCC VIN 5.2V LDO REG + - 12 B 0.8V 4 FCB FC - + TOP F BOOST 15 TG 16 SW BOT SWITCH LOGIC 14 D1 CB UVL INTVCC DB VSEC + CIN + CSEC - + - 6mV + + COUT BURST DISABLE FC A + CINTVCC INTVCC BUFFERED ITH 30k 30k 4.8V BG 11 PGND SENSE + 8 7 SENSE - EXTVCC 9 10 RSENSE 1735 FD LTC1735 OPERATIO Main Control Loop The LTC1735 uses a constant frequency, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle when the oscillator sets the RS latch and turned off when the main current comparator I1 resets the RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on Pin 3 (ITH), which is the output of error amplifier EA. Pin 6 (VOSENSE), described in the pin functions, allows EA to receive an output feedback voltage VFB from an external resistive divider. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from INTVCC through an external diode when the top MOSFET is turned off. As VIN decreases towards VOUT, the converter will attempt to turn on the top MOSFET continuously ("dropout''). A dropout counter detects this condition and forces the top MOSFET to turn off for about 500ns every tenth cycle to recharge the bootstrap capacitor. The main control loop is shut down by pulling Pin 2 (RUN/SS) low. Releasing RUN/SS allows an internal 2A current source to charge soft-start capacitor CSS. When CSS reaches 1.3V, the main control loop is enabled with the ITH voltage clamped at approximately 30% of its maximum value. As CSS continues to charge, ITH is gradually released allowing normal operation to resume. If VOUT has not reached 70% of its final value when CSS has charged to 4.1V, latchoff can be invoked as described in the Applications Information section. The internal oscillator can be synchronized to an external clock applied to the FCB pin and can lock to a frequency between 90% and 130% of its nominal rate set by capacitor COSC. An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious condi- U (Refer to Functional Diagram) tions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Foldback current limiting for an output shorted to ground is provided by amplifier A. As VOSENSE drops below 0.6V, the buffered ITH input to the current comparator is gradually pulled down to a 0.86V clamp. This reduces peak inductor current to about 1/4 of its maximum value. Low Current Operation The LTC1735 has three low current modes controlled by the FCB control pin. Burst Mode operation is selected when the FCB pin is above 0.8V (typically tied to INTVCC). In Burst Mode operation, if the error amplifier drives the ITH voltage below 0.86V, the buffered ITH input to the current comparator will be clamped at 0.86V. The inductor current peak is then held at approximately 20mV/RSENSE (about 1/4 of maximum output current). If ITH then drops below 0.5V, the Burst Mode comparator B will turn off both MOSFETs to maximize efficiency. The load current will be supplied solely by the output capacitor until ITH rises above the 50mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by comparator F when the FCB pin is brought below 0.8V. This forces continuous operation and can assist secondary winding regulation. When the FCB pin is driven by an external oscillator, a cycle-skipping operation is invoked and the internal oscillator is synchronized to the external clock by comparator C. In this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency operation. The FCB pin is tied to ground when forced continuous operation is desired. This operation is the least efficient mode, but is desirable in certain applications. The output can source or sink current in this mode. When forcing continuous operation and sinking current, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels-- BEWARE. 5 LTC1735 OPERATIO Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff The RUN/SS capacitor, CSS, is used initially to limit the inrush current of each switching regulator. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, CSS is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This builtin latchoff can be overridden by providing a >5A pull-up at a compliance of 4V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of CSS during an overcurrent and/or short-circuit condition. Foldback current limiting is activated when the APPLICATIO S I FOR ATIO The basic LTC1735 application circuit is shown in Figure 1 on the first page. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, COSC and L can be chosen. Next, the power MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired amount of ripple current. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple specification. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection for Output Current RSENSE is chosen based on the required output current. The LTC1735 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.5(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, IL. 6 U W U U U (Refer to Functional Diagram) output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. INTVCC/EXTVCC POWER Power for the top and bottom MOSFET drivers and most of the internal circuitry of the LTC1735 is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5.2V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC is raised above 4.7V, the internal regulator is turned off and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source, such as the primary or a secondary output of the converter itself, to provide the INTVCC power. To provide clean start-up and to protect the MOSFETs, undervoltage lockout is used to keep both MOSFETs off until the input voltage is above 3.5V. Allowing a margin for variations in the LTC1735 and external component values yields: RSENSE = 50mV IMAX COSC Selection for Operating Frequency and Synchronization The choice of operating frequency and inductor value is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The LTC1735 uses a constant frequency architecture with the frequency determined by an external oscillator capacitor COSC. Each time the topside MOSFET turns on, the voltage on COSC is reset to ground. During the on-time, COSC is charged by a fixed current. When the voltage on the LTC1735 APPLICATIO S I FOR ATIO capacitor reaches 1.19V, COSC is reset to ground. The process then repeats. The value of COSC is calculated from the desired operating frequency assuming no external clock input on the FCB pin: 1.61(107 ) - 11 COSC (pF) = Frequency A graph for selecting COSC versus frequency is shown in Figure 2. The maximum recommended switching frequency is 550kHz . The internal oscillator runs at its nominal frequency (fO) when the FCB pin is pulled high to INTVCC or connected to ground. Clocking the FCB pin above and below 0.8V will cause the internal oscillator to injection lock to an external clock signal applied to the FCB pin with a frequency between 0.9fO and 1.3fO. The clock high level must exceed 1.3V for at least 0.3s and the clock low level must be less than 0.3V for at least 0.3s. The top MOSFET turn-on will synchronize with the rising edge of the clock. Attempting to synchronize to too high of an external frequency (above 1.3fO) can result in inadequate slope compensation and possible loop instability. If this condition exists simply lower the value of COSC so fEXT = fO according to Figure 2. When synchronized to an external clock, Burst Mode operation is disabled but the inductor current is not allowed to reverse. The 25% minimum inductor current 100.0 87.5 75.0 COSC VALUE (pF) 62.5 50.0 37.5 25.0 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHZ) 600 1735 F02 Figure 2. Timing Capacitor Value U clamp present in Burst Mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant frequency operation is not as efficient as Burst Mode operation, but does provide a lower noise, constant frequency spectrum. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: W U U IL = V 1 VOUT 1 - OUT ( f)(L) VIN Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.4(IMAX). Remember, the maximum IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Lower inductor values (higher IL) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy 7 LTC1735 APPLICATIO S I FOR ATIO or Kool M(R) cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates "hard," which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool M. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1735: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.2V during start-up (see EXTVCC pin connection). Consequently, logic-level threshold MOSFETs must be used in most LTC1735 applications. The only exception is when low input voltage is expected (VIN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the "ON" resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1735 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: 8 U V Main Switch Duty Cycle = OUT VIN W U U V -V Synchronous Switch Duty Cycle = IN OUT VIN The MOSFET power dissipations at maximum output current are given by: 2 V PMAIN = OUT IMAX 1 + RDS(ON) + VIN ( )( ) k VIN ( ) (IMAX )(CRSS )(f) 2 2 V -V PSYNC = IN OUT IMAX 1 + RDS(ON) VIN ( )( ) where is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is Kool M is a registered trademark of Magnetics, Inc. LTC1735 APPLICATIO S I FOR ATIO generally a good size for 3A to 5A regulators. The diode may be omitted if the efficiency can be tolerated. CIN and COUT Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: V V IRMS IO(MAX ) OUT IN - 1 VIN VOUT 1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. The selection of COUT is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. The output ripple (VOUT) is determined by: 1 VOUT IL ESR + 4fCOUT Where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the I RIPPLE(P-P) requirement. With IL = 0.4IOUT(MAX) the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2 RSENSE COUT > 1/(2fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guaran- U tees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin loop compensation components can be modified to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface-mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface-mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface-mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. W U U 9 LTC1735 APPLICATIO S I FOR ATIO INTVCC Regulator An internal P-channel low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1735. The INTVCC pin can supply a maximum RMS current of 50mA and must be bypassed to ground with a minimum of 4.7F tantalum, 10F special polymer or low ESR type electrolytic capacitor. Good bypassing is required to supply the high transient currents required by the MOSFET gate drivers. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1735 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional loading of INTVCC also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5.2V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5.2V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC) and overall efficiency is lowered. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1735CS is limited to less than 17mA from a 30V supply when not using the EXTVCC pin as follows: TJ = 70C + (17mA)(30V)(110C/W) = 126C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70C + (17mA)(5V)(110C/W) = 79C To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC1735 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. Whenever the EXTVCC pin is above 4.7V the internal 5.2V regulator shuts off, the switch closes and INTVCC power is supplied via EXTVCC until EXTVCC drops below 4.5V. This 10 U allows the MOSFET gate drive and control power to be derived from the output or other external source during normal operation. When the output is out of regulation (start-up, short-circuit) power is supplied from the internal regulator. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for 3.3V and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.2V regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. EXTVCC connected directly to VOUT. This is the normal connection for a 5V regulator and provides the highest efficiency. 3. EXTVCC connected to an output-derived boost network. For 3.3V and other low voltage regulators, efficiency gains can still be realized by connecting EXTVCC to an outputderived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding as shown in Figure 3a or the capacitive charge pump shown in Figure 3b. The charge pump has the advantage of simple magnetics. 4. EXTVCC connected to an external supply. If an external supply is available in the 5V to 7V range (EXTVCC VIN), it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. Output Voltage Programming The output voltage is set by an external resistive divider according to the following formula: W U U R2 VOUT = 0.8 V 1 + R1 LTC1735 APPLICATIO S I FOR ATIO The resistive divider is connected to the output as shown in Figure 4 allowing remote voltage sensing. VOUT R2 VOSENSE LTC1735 SGND 1735 F04 100pF R1 EXTVCC R4 FCB R3 BG N-CH SGND PGND SW L1 1:N Figure 4. Setting the LTC1735 Output Voltage Topside MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. Note that the voltage across CB is about a diode drop below INTVCC. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage SW rises to VIN and the BOOST pin rises to VIN + INTVCC. The value of the boost capacitor CB needs to be 100 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1F to 0.33F is adequate. The reverse breakdown on DB must be greater than VIN(MAX). When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. SENSE +/SENSE - Pins The common mode input range of the current comparator is from 0V to 1.5(INTVCC). Continuous linear operation in step-down applications is guaranteed throughout this range allowing output voltages anywhere from 0.8V to 7V. A differential NPN input stage is used and is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This causes current to either be sourced or sunk by the sense pins depending on the output voltage. If the output voltage is below 2.4V current U VIN OPTIONAL EXTVCC CONNECTION 5V VSEC 7V VIN LTC1735 TG RSENSE VOUT N-CH W U U + CIN 1N4148 VSEC + 1F + COUT 1735 F03a Figure 3a. Secondary Output Loop and EXTVCC Connection VIN + 1F + CIN VIN LTC1735 TG N-CH VN2222LL RSENSE VOUT EXTVCC SW L1 BAT85 BAT85 0.22F BAT85 + BG N-CH PGND 1735 F03b COUT Figure 3b. Capacitive Charge Pump for EXTVCC will flow out of both sense pins to the main output. This forces a minimum load current that can be fulfilled by the VOUT resistive divider. The maximum current flowing out of the sense pins is: ISENSE+ + ISENSE- = (2.4V - VOUT)/24k Since VOSENSE is servoed to the 0.8V reference voltage, we can choose R1 in Figure 4 to have a maximum value to absorb this current: 0.8 V R1(MAX ) = 24k 2.4V - VOUT 11 LTC1735 APPLICATIO S I FOR ATIO Regulating an output voltage of 1.8V, the maximum value of R1 should be 32k. Note that at output voltages above 2.4V no maximum value of R1 is necessary to absorb the sense pin currents; however, R1 is still bounded by the VOSENSE feedback current. Soft-Start/Run Function The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC1735. Soft-start reduces surge currents from VIN by gradually increasing the controller's current limit ITH(MAX). This pin can also be used for power supply sequencing. Pulling the RUN/SS pin below 1.3V puts the LTC1735 into a low quiescent current shutdown (IQ < 20A). This pin can be driven directly from logic as shown in Figure 5. Releasing the RUN/SS pin allows an internal 2A current source to charge up the external RUN/SS capacitor CSS. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: TDELAY = 1.3V CSS = 650ms / F CSS 2A ( ) When the voltage on RUN/SS reaches 1.3V the LTC1735 begins operating with a current limit at approximately 25mV/RSENSE. As the voltage on the RUN/SS pin increases from 1.3V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 850ms/F to reach full current. The output current thus ramps up slowly, reducing the starting surge current required from the input power supply. Diode D1 in Figure 5 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. This diode and CSS can be deleted if soft-start is not needed. The RUN/SS pin has an internal 6V zener clamp (See Functional Diagram). 3.3V OR 5V D1 CSS CSS RUN/SS RUN/SS Figure 5. RUN/SS Pin Interfacing 12 U Fault Conditions: Overcurrent Latchoff The RUN/SS pin also provides the ability to shut off the controller and latch off when an overcurrent condition is detected. The RUN/SS capacitor CSS is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge up the output capacitor and provide full load current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of it's nominal output voltage after CSS reaches 4.1V, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing >5A at a compliance of 4V to the RUN/SS pin as shown in Figure 6. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5A current from VIN as in Figure 6a, current latchoff is always defeated. Diode connecting this pull-up resistor to INTVCC , as in Figure 6b, eliminates any extra supply current during controller shutdown while eliminating the INTVCC loading from preventing controller start-up. If the voltage on CSS does not exceed 4.1V the overcurrent latch is not armed and the function is disabled. Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal shortcircuit and foldback current limiting still remains active, VIN 3.3V OR 5V D1 RSS RUN/SS RSS D1 CSS CSS RUN/SS INTVCC 1735 F05 W U U (a) (b) 1735 F06 Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated LTC1735 APPLICATIO S I FOR ATIO thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. The value of the soft-start capacitor CSS will need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10 - 4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1F will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1735 current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The LTC1735 includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is defeated. If the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mV to 30mV. Under short-circuit conditions with very low duty cycle, the LTC1735 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be conducting the peak current. The short-circuit ripple current is determined by the minimum on-time TON(MIN) of the LTC1735 (approximately 200ns), the input voltage and inductor value: IL(SC) = TON(MIN)VIN/L The resulting short-circuit current is: ISC = 30mV 1 + IL(SC) RSENSE 2 The current foldback function is always active and is not effected by the current latchoff function. Fault Conditions: Output Overvoltage Protection (Crowbar) The output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the U regulator rises much higher than nominal levels. This condition causes huge currents to flow, much greater than in normal operation. This feature is designed to protect against a shorted top MOSFET; it does not protect against a failure of the controller itself. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed the top MOSFET is turned off and the bottom MOSFET is forced on. The bottom MOSFET remains on continuously for as long as the 0V condition persists; if VOUT returns to a safe level, normal operation automatically resumes. Minimum On-Time Considerations Minimum on-time TON(MIN) is the smallest amount of time that the LTC1735 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit and care should be taken to ensure that: V TON(MIN) < OUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1735 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and voltage will increase. The minimum on-time for the LTC1735 in a properly configured application is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule keep the inductor ripple current equal or greater than 30% of IOUT(MAX) at VIN(MAX). W U U 13 LTC1735 APPLICATIO S I FOR ATIO FCB Pin Operation When the FCB pin drops below its 0.8V threshold, continuous mode operation is forced. In this case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. In addition to providing a logic input to force continuous synchronous operation and external synchronization, the FCB pin provides a means to regulate a flyback winding output. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom, synchronous switch is on. When primary load currents are low and/or the VIN/ VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings providing there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in Figure 3a by the turns ratio N of the transformer: VSEC (N + 1)VOUT However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): R4 VSEC(MIN) 0.8 V 1 + R3 If VSEC drops below this level, the FCB voltage forces continuous switching operation until VSEC is again above its minimum. In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.25A internal current source pulling the pin high. Remember to 14 U include this current when choosing resistor values R3 and R4. The internal LTC1735 oscillator can be synchronized to an external oscillator by applying and clocking the FCB pin with a signal above 1.5VP-P. When synchronized to an external frequency, Burst Mode operation is disabled but cycle skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to assure the bootstrap cap is kept refreshed. The rising edge of an external clock applied to the FCB pin starts a new cycle. The range of synchronization is from 0.9fO to 1.3fO, with fO set by COSC. Attempting to synchronize to a higher frequency than 1.3fO can result in inadequate slope compensation and cause loop instability with high duty cycles (duty cycle > 50%). If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC. The following table summarizes the possible states available on the FCB pin: Table 1 FCB Pin DC Voltage: 0V to 0.7V DC Voltage: 0.9V Feedback Resistors Ext Clock: (0V to VFCBSYNC) (VFCBSYNC > 1.5V) Condition Burst Disabled/Forced Continuous Current Reversal Enabled Burst Mode Operation, No Current Reversal Regulating a Secondary Winding Burst Mode Operation Disabled No Current Reversal W U U Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, 5 main sources usually account for most of the LTC1735 APPLICATIO S I FOR ATIO losses in LTC1735 circuits: 1) LTC1735 VIN current, 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET transition losses, 5) Other losses. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN. 2) INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT+QB), where QT and QB are the gate charges of the topside and bottom-side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V application, 10mA of INTVCC current results in approximately 3mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3) I2R losses are predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode the average output current flows through L and RSENSE, but is "chopped" between the topside main MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.03, RL = 0.05 and RSENSE = 0.01, then the total resistance is 0.09. This results in losses ranging from 2% to 9% as the output current increases from 1A to 5A for a 5V output, or a 3% to 14% loss for a 3.3V output. Effeciency varies as the inverse square of VOUT for the same external components and output power level. I2R losses cause the efficiency to drop at high output currents. 4) Transition losses apply only to the topside MOSFET(s) U and only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss = (1.7) VIN2 IO(MAX) CRSS f 5) Other "hidden" losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these "system" level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 0.01 to 0.02 of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to maximize W U U 15 LTC1735 APPLICATIO S I FOR ATIO transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than1:50, the switch rise time should be controlled so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA. Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main battery line in an automobile is the source of a number of nasty potential transients, including load-dump, reverse-battery and double-battery. 16 U Load-dump is the result of a loose battery cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse-battery is just what it says, while double-battery is a consequence of tow-truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 7 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive battery line. The series diode prevents current from flowing during reverse-battery, while the transient suppressor clamps the input voltage during load-dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1735 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. 50A IPK RATING 12V W U U VIN LTC1735 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 1735 F07 Figure 7. Plugging into the Cigarette Lighter Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A and f = 300kHz. RSENSE and COSC can immediately be calculated: RSENSE = 50mV/5A = 0.01 COSC = 1.61(107)/(300kHz) - 11pF = 43pF Assume a 3.3H inductor and check the actual value of the ripple current. The following equation is used: V V IL = OUT 1 - OUT VIN ( f)(L) The highest value of the ripple current occurs at the maximum input voltage: LTC1735 APPLICATIO S I FOR ATIO 1.8 V 1.8 V IL = 1- = 2.3A 300kHz(3.3H) 22V The maximum ripple current is 33% of maximum output current, which is about right. Next verify the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VOUT VIN(MAX )f = 1.8 V = 273ns 22V(300kHz) Since the output voltage is below 2.4V the output resistive divider will need to be sized to not only set the output voltage but also to absorb the sense pin current. 0.8 V R1(MAX ) = 24k 2.4V - VOUT 0.8 V = 24K = 32k 2.4V - 1.8 V Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. The power dissipation on the topside MOSFET can be easily estimated. Choosing a Siliconix Si4412DY results in RDS(ON) = 0.042, CRSS = 100pF. At maximum input voltage with T(estimated) = 50C: PMAIN = = 220mW ()[ ]( 2 +1.7(22V ) (5A )(100pF )(300kHz) 1.8 V 2 5 1 + (0.005)(50C - 25C) 0.042 22V Because the duty cycle of the bottom MOSFET is much greater than the top, a larger MOSFET, Siliconix Si4410, (RDS(ON) = 0.02) is chosen. The power dissipation in the bottom MOSFET, again assuming T = 50C, is: PSYNC = 2 22V - 1.8 V 5A 1.1 0.02 22V = 500mW ( ) ( )( ) U Thanks to current foldback, the bottom MOSFET dissipation in short-circuit will be less than under full load conditions. CIN is chosen for an RMS current rating of at least 2.5A at temperature. COUT is chosen with an ESR of 0.02 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The worst-case output voltage ripple due to ESR is approximately: VORIPPLE = RESR(IL) = 0.02(2.3A) = 46mVP-P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1735. These items are also illustrated graphically in the layout diagram of Figure 8. Check the following in your layout: 1) Are the signal and power grounds segregated? The LTC1735 signal ground pin must return to the (-) plate of COUT. The power ground connects to the source of the bottom N-channel MOSFET, anode of the Schottky diode and (-) plate of CIN, which should have as short lead lengths as possible. 2) Does the VOSENSE pin connect directly to the feedback resistors? The resistive divider R1, R2 must be connected between the (+) plate of COUT and signal ground. The 100pF capacitor should be as close as possible to the LTC1735. 3) Are the SENSE - and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE - should be as close as possible to the LTC1735. 4) Does the (+) plate of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). 5) Is the INTVCC decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. 6) Keep the switching node (SW), top gate node (TG) and boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast W U U ) 17 LTC1735 APPLICATIO S I FOR ATIO moving signals and therefore should be kept on the "output side" (Pin 9 to Pin 16) of the LTC1735 and occupy minimum PC trace area. + COSC 1 CSS 2 RC CC2 4 FCB CC 3 ITH LTC1735 VIN 13 DB CB D1 SW 14 VIN COSC TG 16 M1 5 100pF 6 SGND INTVCC 12 VOSENSE SENSE - SENSE + BG 11 + 4.7F M2 7 1000pF 8 PGND 10 + RUN/SS EXTVCC R2 Figure 8. LTC1735 Layout Diagram TYPICAL APPLICATIO S 1.8V/5A Converter from Design Example VIN 4.5V TO 22V COSC 43pF 1 CSS 0.1F 2 RC 10k CC2 51pF 4 CC 330pF 3 COSC TG 16 CB 0.1F 15 M1 Si4412DY RUN/SS BOOST ITH LTC1735 FCB SW 14 L1 3.3H RSENSE 0.01 R2 32.4k 1% 4.7F M2 Si4410 MBRS140T3 R1 25.5k 1% SGND VOUT 1.8V 5A VIN 13 DB CMDSH-3 5 100pF 6 SGND INTVCC 12 + 11 VOSENSE SENSE - SENSE + BG 7 1000pF 8 PGND 10 EXTVCC 9 OPTIONAL: CONNECT TO 5V 18 + U BOOST 15 CIN - 9 L1 - R1 COUT RSENSE + 1735 F08 W U U U VOUT + CIN 22F 35V X3 + COUT 150F 6.3V X2 1735 TA02 LTC1735 TYPICAL APPLICATIO S Selectable Output Voltage Converter with Burst Mode Operation Disabled for CPU Power VIN 4.5V TO 24V COSC 56pF 1 CSS 0.1F 2 RC 10k CC2 51pF 4 CC 680pF 3 COSC TG 16 CB 0.22F 15 M1 FDS6680A RUN/SS ITH LTC1735 FCB 5 100pF 6 SGND VOSENSE SENSE - SENSE + 7 1000pF 8 COSC 50pF 1 CSS 0.1F 2 RC 10k CC2 51pF 4 CC 510pF 3 COSC TG 16 CB 0.1F 15 M1 IRF7803 RUN/SS ITH LTC1735 FCB 5 100pF 6 SGND VOSENSE SENSE - SENSE + 7 1000pF 8 100 100 10k 90.9k 1735 TA04 U + CIN 10F 30V X3 BOOST SW 14 L1 1.5H RSENSE 0.0045 R2 12.4k 1% 4.7F M2 FDS6680A X2 MBRD835L R3 64.9k 1% R1 20k 1% VOUT 1.3V/1.45V 12A VIN 13 DB CMDSH-3 INTVCC 12 + 11 + BG COUT 150F 6.3V X3 PGND 10 ON: VOUT = 1.45V OFF: VOUT = 1.30V 9 OPTIONAL: CONNECT TO 5V SGND 1735 TA05 EXTVCC 5V/3.5A Converter with 12V/200mA Auxiliary Output VIN 5.5V TO 28V + CIN 10F 30V X2 22 MBRS1100T3 1000pF BOOST SW 14 + 13 DB CMDSH-3 T1 10H RSENSE 0.012 VIN CSEC 22F 25V R2 105k 1% VOUT 5V 3.5A INTVCC 12 + 4.7F 11 M2 IRF7803 MBRS140T3 + BG R1 20k 1% SGND COUT 100F 10V X3 PGND 10 EXTVCC 9 VOUT2 12V UNREG 19 LTC1735 TYPICAL APPLICATIO 3.3V/5A Converter with External Clock Synchronization Operating at 500kHz VIN 4.5V TO 28V COSC 20pF 1 CSS 0.1F 2 RC 10k CC2 51pF EXT CLOCK 500kHz 100pF 6 VOSENSE SENSE - SENSE + BG 11 4 CC 330pF 3 COSC TG 16 CB 0.1F 15 M1 Si4410DY RUN/SS ITH LTC1735 FCB 5 SGND 7 1000pF 8 RELATED PARTS PART NUMBER LTC1147 LTC1148HV/LTC1148 LTC1149 LTC1159 LTC1174 LTC1265 LTC1266 LT1375/LT1376 LTC1433/LTC1434 LTC1435 LTC1436/LTC1436-PLL LTC1474/LTC1475 LTC1625 LTC1627 LTC1628 LTC1736 DESCRIPTION High Efficiency Step-Down Controller High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller High Efficiency Synchronous Step-Down Controller Monolithic 0.6A Step-Down Switching Regulator 1.2A Monolithic High Efficiency Step-Down Switching Regulator High Efficiency Synchronous Step-Down Controller, N-Ch Drive 1.5A 500kHz Step-Down Switching Regulator Monolithic 0.45A Low Noise Current Mode Step-Down Switching Regulator High Efficiency Low Noise Synchronous Step-Down Controller, N-Ch Drive High Efficiency Low Noise Synchronous Step-Down Converter, N-Ch Drive Ultralow Quiescent Current Step-Down Monolithic Switching Regulator No RSENSE Current Mode Synchronous Step-Down Controller Synchronous Monolithic 0.5A Step-Down Regulator Dual High Efficiency Step-Down Controller High Efficiency Step-Down Controller with VID Control TM No RSENSE is trademark of Linear Technology Corporation. 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com U + CIN 22F 35V X3 BOOST SW 14 L1 4.7H RSENSE 0.01 R2 62.6k 1% 4.7F M2 Si4410DY MBRS140T3 R1 20k 1% SGND EXTVCC 9 OPTIONAL: CONNECT TO 5V VOUT 3.3V 5A VIN 13 DB CMDSH-3 INTVCC 12 + + COUT 100F 10V X3 PGND 10 1735 TA06 COMMENTS 100% DC, Burst Mode Operation, 8-Pin 100% DC, Burst Mode Operation, VIN < 20V 100% DC, Std Threshold MOSFETs, VIN < 48V 100% DC, Logic Level MOSFETs, VIN < 40V 100% DC, Burst Mode Operation, 8-Pin SO 100% DC, Burst Mode Operation, 14-Pin SO 100% DC, Burst Mode Operation, VIN < 20V High Efficiency, Monolithic 16-Pin Narrow, 20-Pin Narrow SSOP Burst Mode Operation, 16-Pin Narrow SO Adaptive Power Mode 20-Pin, 24-Pin SSOP 100% DC, 8-Pin MSOP Burst Mode Operation, GN-16 100% DC, SO-8 Antiphase Drive Output Fault Protection, GN-24 1735p LT/TP 1298 * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1998 |
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